Senior IP Design Verification Engineer – XBAR IP
A senior-level role focused on the design verification of crossbar (XBAR) IP blocks, requiring deep expertise in IP-level verification methodologies and digital design principles.
About the role
This is a senior individual-contributor position within the IP design verification domain, specifically focused on crossbar (XBAR) IP. The role demands a strong foundation in functional verification of complex digital IP blocks at the block and subsystem level.
The successful candidate will be responsible for developing and executing comprehensive verification plans, building testbenches, and ensuring the correctness and robustness of XBAR IP designs through rigorous simulation and formal methods.
- Domain: Crossbar (XBAR) IP design verification
- Seniority: Senior Engineer
- Core focus: IP-level functional verification of digital hardware
Candidates should bring hands-on experience with industry-standard verification languages and methodologies such as SystemVerilog and UVM, along with a solid understanding of interconnect and crossbar architectures relevant to high-performance computing or graphics hardware.