Senior IP Design Verification Engineer – XBAR IP
A senior-level role focused on design verification of crossbar (XBAR) IP, requiring deep expertise in digital design verification methodologies and IP-level validation workflows.
About the role
This is a senior individual-contributor position within the IP design verification domain, with a specific focus on crossbar (XBAR) interconnect IP. The role involves owning and driving verification activities for complex XBAR IP blocks from planning through sign-off.
Key responsibilities include:
- Verification planning and execution for XBAR IP, including coverage closure and regression management
- Development of testbenches using industry-standard methodologies such as UVM
- Collaboration with design and architecture teams to understand functional specifications and translate them into comprehensive verification plans
- Debug and root-cause analysis of failures identified during simulation and formal verification
Candidates are expected to bring strong hands-on experience in SystemVerilog and UVM-based verification, a solid understanding of interconnect or bus-fabric IP (such as crossbar, NoC, or AXI/CHI protocols), and the ability to work independently on complex verification challenges in a high-performance engineering environment.
This position suits an experienced verification engineer looking to contribute to cutting-edge silicon IP development at a senior level.