Senior IP Design Verification Engineer – XBAR IP
NVIDIA is seeking a Senior IP Design Verification Engineer specialising in XBAR IP to join its team in Bengaluru, Karnataka. The role focuses on verifying high-performance crossbar interconnect IP designs.
About the role
This is a senior-level engineering opportunity within NVIDIA's hardware design organisation, focused on the verification of XBAR (crossbar) IP — a critical component in high-speed, high-bandwidth chip architectures. The successful candidate will be responsible for ensuring the functional correctness and robustness of complex interconnect IP blocks.
Key Responsibilities
- Develop and execute comprehensive verification plans for XBAR IP designs.
- Build and maintain constrained-random testbenches and functional coverage models.
- Collaborate closely with design engineers to understand microarchitecture and identify verification gaps.
- Debug simulation failures, analyse root causes, and drive issues to closure.
- Contribute to the continuous improvement of verification methodologies and flows.
Candidate Profile
- Demonstrated experience in IP-level design verification, preferably involving interconnect or fabric IP.
- Strong proficiency in SystemVerilog and UVM-based verification environments.
- Solid understanding of digital design fundamentals and bus/interconnect protocols.
- Ability to work independently and as part of a collaborative, cross-functional team.
This position is based in Bengaluru, Karnataka, and offers the opportunity to work on industry-leading silicon that powers some of the world's most advanced computing platforms.