Senior IP Design Verification Engineer – XBAR IP
A senior-level role focused on design verification of XBAR IP, requiring deep expertise in IP verification methodologies and digital design principles.
About the role
This is a Senior IP Design Verification Engineer position specialising in XBAR IP. The role sits within the hardware engineering function and is focused on verifying complex interconnect IP blocks to ensure correctness, performance, and reliability.
Candidates are expected to bring strong hands-on experience in IP-level design verification, including the development and execution of verification plans, testbenches, and coverage models for high-speed interconnect or bus-fabric IP.
The position demands a thorough understanding of industry-standard verification methodologies and proficiency in hardware description and verification languages commonly used in the semiconductor domain.