Senior IP Design Verification Engineer – XBAR IP
A senior-level role focused on design verification of crossbar (XBAR) IP, requiring deep expertise in digital design verification methodologies and IP-level validation within a semiconductor environment.
About the role
The employer is seeking a Senior IP Design Verification Engineer to join its XBAR IP team. This role centres on the verification of crossbar interconnect IP, a critical component in high-performance semiconductor design.
The position requires hands-on experience with IP-level design verification, including developing and executing verification plans, writing testbenches, and validating complex digital logic. Candidates should have a strong background in industry-standard verification methodologies such as UVM/SystemVerilog.
Key responsibilities are expected to include:
- Developing and maintaining verification environments for XBAR IP blocks
- Defining coverage models and closure strategies
- Collaborating with design and architecture teams to ensure functional correctness
- Debugging and root-causing failures across simulation and emulation platforms
This is a senior individual-contributor opportunity suited to engineers with substantial experience in RTL design verification within the semiconductor or SoC domain.