Formal Verification Engineer – AI Hardware
A Formal Verification Engineer is sought to work on AI hardware projects, applying formal methods to ensure the correctness and reliability of complex chip designs.
About the role
This role is focused on formal verification of hardware designs within an AI-driven engineering environment. The successful candidate will be responsible for applying formal methods and property-checking techniques to validate the functional correctness of complex digital designs.
Key responsibilities include:
- Formal property verification of RTL designs using industry-standard tools and methodologies
- Developing and maintaining assertion-based verification environments
- Collaborating closely with design and validation teams to identify and resolve functional issues early in the development cycle
- Contributing to the definition of verification plans and sign-off criteria for complex hardware blocks
Candidates are expected to have a strong background in digital design verification, with hands-on experience in formal verification tools and languages such as SystemVerilog and SVA. Familiarity with hardware design flows and a solid understanding of computer architecture are considered essential for this position.
This is an opportunity to contribute to cutting-edge AI hardware development, working alongside experienced engineering teams on technically challenging and high-impact projects.