Formal Verification Engineer
A Formal Verification Engineer role focused on applying rigorous mathematical and logic-based techniques to verify hardware or software designs, ensuring correctness and reliability.
About the role
This position is for a Formal Verification Engineer who will be responsible for applying formal methods to verify the correctness of complex designs. The role demands a strong foundation in formal verification techniques and the ability to work within a high-performance engineering environment.
The ideal candidate will bring expertise in formal property checking, model checking, equivalence checking, or related methodologies. Experience with industry-standard formal verification tools and hardware description languages is expected.
- Apply formal verification methods to validate design correctness
- Develop and maintain formal testbenches, properties, and constraints
- Collaborate with design and validation teams to identify and resolve issues
- Contribute to the improvement of formal verification flows and methodologies
Candidates should possess a solid understanding of digital design principles and have hands-on experience with formal verification in a professional or research setting. A background in computer engineering, electrical engineering, or a related discipline is typically required for this role.